By joining us, you will collaborate with the world's leading CPU research team to design low-power and high-performance CPU products. Your job responsibilities include, but are not limited to:
System-Level Requirement Analysis: Collaborate with architects and designers to break down SoC requirements, formulate FCH validation strategies, and create executable test plans.
Integration & Functional Validation: Develop and execute diagnostics and test cases on simulation, emulation, FPGA, and silicon platforms to validate FCH features such as USB, SATA, PCIe, and other I/O protocols.
Test Package Development: Release ATE (Automated Test Equipment) test vector packages, including functional, stress, corner, and shmoo tests for FCH I/O coverage and performance.
Performance Profiling & Characterization: Prepare and execute silicon power/performance profiling test cases for all FCH paths and monitor interactions with CPU/system.
Debug & Silicon Issue Localization: Rapidly identify, reproduce, and isolate FCH issues during validation cycles; expand and maintain a silicon diagnostic test suite for quick bug detection.
Cross-Functional Collaboration: Work closely with DV, firmware, and platform teams to resolve issues across RTL, software, and real-silicon domains.
任职要求
Familiarity with x86 architectures (preferred), and knowledge of ARM/RISC-V is a plus.
Strong knowledge of southbridge/I/O subsystems: PCIe, USB (2.0/3.x), SATA, networking, GPIO, etc.
Solid background in laboratory validation (oscilloscopes, protocol analyzers, logic analyzers).
Programming skills in C/C++ and scripting languages (Python or Shell).
Experience in FPGA/emulation validation platforms; hands-on experience with relevant hardware debug tools (e.g., TRACE32) is preferred.
Practical knowledge of bring-up and debug for I/O protocols at both hardware and firmware levels.
Familiarity with test vector generation and production silicon validation flows is a plus.
Strong analytical and troubleshooting ability for complex SoC systems.
Excellent communication skills for cross-team coordination.
Adaptability and self-motivation in a dynamic R&D environment.
Academic Credentials:
Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or related disciplines.
5+ years of hands-on experience in SoC or I/O subsystem validation, chip bring-up, or related fields.
