1. Perform block level analog layout. Conduct physical verification (ANT、DRC and LVS using Cadence tools) and RC extraction.
2. Independent IP analog layout. Conduct physical verification (ANT、DRC and LVS using Cadence tools) and RC extraction. EMIR optimization .Generate CDK for IP.
3. Testchip Layout verification of the layout (ANT/DRC/ERC/LVS).Date and package netlist for chip layout.
4. Team work with analog designers, optimize layout..
任职要求
1. Familliar with layout skills and knowledge is must.
2. Good teamwork/communication/positive is must.
3. Familiar with Cadence IC layout and verification tools
4. Familiar with 0.18/0.13/0.04/0.055/0.028/0.0014 um CMOS process and design rule is a plus.
5. Familiar with ESD/Latch up/antenna and related layout solutions is a plus.
6. Familiar with rule deck is a plus.
*公司坚持平等原则，公平公正对待不同背景的员工，包含但不限于国籍、性别、宗教信仰、文化背景等方面，提供平等发展机会，构建多元化人才体系
