Responsibilities:
The candidate is expected to be responsible for following tasks
1. Participate in SOC full chip DFT feature and architecture definition;
2. Implement SOC DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test logic;
3. Generate DFT related timing constraints and work for timing closure;
4. Develop and verify high coverage and cost-effective test patterns for the production test;
5.Evaluate and establish the advanced DFT tools and flow.
Qualifications:
1. 8+ years’ experience for Bachelor or 5+ years for Master in DFT design and verification, test pattern development;
2. Good Knowledge of Scan/ATPG, MBIST and boundary scan and other DFT techniques;
3. Good Knowledge of industry DFT tools like DFTMax, TetraMax ,TestKompress, FastScan, Tessent Mbist, SMS etc.
4. Good knowledge of digital SoC/ASIC design, including STA, verification and RTL coding;
5. Proficient in hardware description languages such as Verilog, System Verilog and VHDL;
6. Good Knowledge of script language, such as Tcl, Python, Perl;
7. Good English communication skills;
8. Strong commitment to schedule and work quality, good team player.
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